LSM6DSO32_interrupt_pins

This section groups all the functions that manage interrupt pins. More...

Collaboration diagram for LSM6DSO32_interrupt_pins:

Functions
int32_t	lsm6dso32_int1_mode_set (stmdev_ctx_t *ctx, lsm6dso32_int1_pd_en_t val)
	Connect/Disconnect INT1 internal pull-down.[set].
int32_t	lsm6dso32_int1_mode_get (stmdev_ctx_t *ctx, lsm6dso32_int1_pd_en_t *val)
	Connect/Disconnect INT1 internal pull-down.[get].
int32_t	lsm6dso32_pin_int1_route_set (stmdev_ctx_t *ctx, lsm6dso32_pin_int1_route_t *val)
	Select the signal that need to route on int1 pad.[set].
int32_t	lsm6dso32_pin_int1_route_get (stmdev_ctx_t *ctx, lsm6dso32_pin_int1_route_t *val)
	Select the signal that need to route on int1 pad.[get].
int32_t	lsm6dso32_pin_int2_route_set (stmdev_ctx_t *ctx, lsm6dso32_pin_int2_route_t *val)
	Select the signal that need to route on int2 pad.[set].
int32_t	lsm6dso32_pin_int2_route_get (stmdev_ctx_t *ctx, lsm6dso32_pin_int2_route_t *val)
	Select the signal that need to route on int2 pad.[get].
int32_t	lsm6dso32_pin_mode_set (stmdev_ctx_t *ctx, lsm6dso32_pp_od_t val)
	Push-pull/open drain selection on interrupt pads.[set].
int32_t	lsm6dso32_pin_mode_get (stmdev_ctx_t *ctx, lsm6dso32_pp_od_t *val)
	Push-pull/open drain selection on interrupt pads.[get].
int32_t	lsm6dso32_pin_polarity_set (stmdev_ctx_t *ctx, lsm6dso32_h_lactive_t val)
	Interrupt active-high/low.[set].
int32_t	lsm6dso32_pin_polarity_get (stmdev_ctx_t *ctx, lsm6dso32_h_lactive_t *val)
	Interrupt active-high/low.[get].
int32_t	lsm6dso32_all_on_int1_set (stmdev_ctx_t *ctx, uint8_t val)
	All interrupt signals become available on INT1 pin.[set].
int32_t	lsm6dso32_all_on_int1_get (stmdev_ctx_t *ctx, uint8_t *val)
	All interrupt signals become available on INT1 pin.[get].
int32_t	lsm6dso32_int_notification_set (stmdev_ctx_t *ctx, lsm6dso32_lir_t val)
	Interrupt notification mode.[set].
int32_t	lsm6dso32_int_notification_get (stmdev_ctx_t *ctx, lsm6dso32_lir_t *val)
	Interrupt notification mode.[get].

Detailed Description

This section groups all the functions that manage interrupt pins.

Function Documentation

lsm6dso32_all_on_int1_get()

int32_t lsm6dso32_all_on_int1_get	(	stmdev_ctx_t *	ctx,
		uint8_t *	val
	)

All interrupt signals become available on INT1 pin.[get].

Parameters

ctx	read / write interface definitions
val	change the values of int2_on_int1 in reg CTRL4_C

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3638 of file lsm6dso32_reg.c.

{
  lsm6dso32_ctrl4_c_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)&reg, 1);
  *val = reg.int2_on_int1;
 
  return ret;
}

References lsm6dso32_ctrl4_c_t::int2_on_int1, LSM6DSO32_CTRL4_C, and lsm6dso32_read_reg().

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lsm6dso32_all_on_int1_set()

int32_t lsm6dso32_all_on_int1_set	(	stmdev_ctx_t *	ctx,
		uint8_t	val
	)

All interrupt signals become available on INT1 pin.[set].

Parameters

ctx	read / write interface definitions
val	change the values of int2_on_int1 in reg CTRL4_C

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3614 of file lsm6dso32_reg.c.

{
  lsm6dso32_ctrl4_c_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.int2_on_int1 = val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}

References lsm6dso32_ctrl4_c_t::int2_on_int1, LSM6DSO32_CTRL4_C, lsm6dso32_read_reg(), and lsm6dso32_write_reg().

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lsm6dso32_int1_mode_get()

int32_t lsm6dso32_int1_mode_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_int1_pd_en_t *	val
	)

Connect/Disconnect INT1 internal pull-down.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of pd_dis_int1 in reg I3C_BUS_AVB

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3077 of file lsm6dso32_reg.c.

{
  lsm6dso32_i3c_bus_avb_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)&reg, 1);
 
  switch (reg.pd_dis_int1)
  {
    case LSM6DSO32_PULL_DOWN_DISC:
      *val = LSM6DSO32_PULL_DOWN_DISC;
      break;
 
    case LSM6DSO32_PULL_DOWN_CONNECT:
      *val = LSM6DSO32_PULL_DOWN_CONNECT;
      break;
 
    default:
      *val = LSM6DSO32_PULL_DOWN_DISC;
      break;
  }
 
  return ret;
}

References LSM6DSO32_I3C_BUS_AVB, LSM6DSO32_PULL_DOWN_CONNECT, LSM6DSO32_PULL_DOWN_DISC, lsm6dso32_read_reg(), and lsm6dso32_i3c_bus_avb_t::pd_dis_int1.

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lsm6dso32_int1_mode_set()

int32_t lsm6dso32_int1_mode_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_int1_pd_en_t	val
	)

Connect/Disconnect INT1 internal pull-down.[set].

Parameters

ctx	read / write interface definitions
val	change the values of pd_dis_int1 in reg I3C_BUS_AVB

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3052 of file lsm6dso32_reg.c.

{
  lsm6dso32_i3c_bus_avb_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.pd_dis_int1 = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)&reg, 1);
  }
 
  return ret;
}

References LSM6DSO32_I3C_BUS_AVB, lsm6dso32_read_reg(), lsm6dso32_write_reg(), and lsm6dso32_i3c_bus_avb_t::pd_dis_int1.

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lsm6dso32_int_notification_get()

int32_t lsm6dso32_int_notification_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_lir_t *	val
	)

Interrupt notification mode.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of lir in reg TAP_CFG0

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3708 of file lsm6dso32_reg.c.

{
  lsm6dso32_tap_cfg0_t tap_cfg0;
  lsm6dso32_page_rw_t page_rw;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
                           (uint8_t *) &tap_cfg0, 1);
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  if (ret == 0)
  {
    switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
    {
      case LSM6DSO32_ALL_INT_PULSED:
        *val = LSM6DSO32_ALL_INT_PULSED;
        break;
 
      case LSM6DSO32_BASE_LATCHED_EMB_PULSED:
        *val = LSM6DSO32_BASE_LATCHED_EMB_PULSED;
        break;
 
      case LSM6DSO32_BASE_PULSED_EMB_LATCHED:
        *val = LSM6DSO32_BASE_PULSED_EMB_LATCHED;
        break;
 
      case LSM6DSO32_ALL_INT_LATCHED:
        *val = LSM6DSO32_ALL_INT_LATCHED;
        break;
 
      default:
        *val = LSM6DSO32_ALL_INT_PULSED;
        break;
    }
 
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_page_rw_t::emb_func_lir, lsm6dso32_tap_cfg0_t::lir, LSM6DSO32_ALL_INT_LATCHED, LSM6DSO32_ALL_INT_PULSED, LSM6DSO32_BASE_LATCHED_EMB_PULSED, LSM6DSO32_BASE_PULSED_EMB_LATCHED, LSM6DSO32_EMBEDDED_FUNC_BANK, lsm6dso32_mem_bank_set(), LSM6DSO32_PAGE_RW, lsm6dso32_read_reg(), LSM6DSO32_TAP_CFG0, and LSM6DSO32_USER_BANK.

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lsm6dso32_int_notification_set()

int32_t lsm6dso32_int_notification_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_lir_t	val
	)

Interrupt notification mode.[set].

Parameters

ctx	read / write interface definitions
val	change the values of lir in reg TAP_CFG0

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3657 of file lsm6dso32_reg.c.

{
  lsm6dso32_tap_cfg0_t tap_cfg0;
  lsm6dso32_page_rw_t page_rw;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
                           (uint8_t *) &tap_cfg0, 1);
 
  if (ret == 0)
  {
    tap_cfg0.lir = (uint8_t)val & 0x01U;
    tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0,
                              (uint8_t *) &tap_cfg0, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
  }
 
  if (ret == 0)
  {
    page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
                              (uint8_t *) &page_rw, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_page_rw_t::emb_func_lir, lsm6dso32_tap_cfg0_t::int_clr_on_read, lsm6dso32_tap_cfg0_t::lir, LSM6DSO32_EMBEDDED_FUNC_BANK, lsm6dso32_mem_bank_set(), LSM6DSO32_PAGE_RW, lsm6dso32_read_reg(), LSM6DSO32_TAP_CFG0, LSM6DSO32_USER_BANK, and lsm6dso32_write_reg().

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lsm6dso32_pin_int1_route_get()

int32_t lsm6dso32_pin_int1_route_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_pin_int1_route_t *	val
	)

Select the signal that need to route on int1 pad.[get].

Parameters

ctx	read / write interface definitions
val	struct of registers: INT1_CTRL, MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3251 of file lsm6dso32_reg.c.

{
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
                             (uint8_t *)&val->emb_func_int1, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_A,
                             (uint8_t *)&val->fsm_int1_a, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_B,
                             (uint8_t *)&val->fsm_int1_b, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT1_CTRL,
                             (uint8_t *)&val->int1_ctrl, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD1_CFG,
                             (uint8_t *)&val->md1_cfg, 1);
  }
 
  return ret;
}

References lsm6dso32_pin_int1_route_t::emb_func_int1, lsm6dso32_pin_int1_route_t::fsm_int1_a, lsm6dso32_pin_int1_route_t::fsm_int1_b, lsm6dso32_pin_int1_route_t::int1_ctrl, LSM6DSO32_EMB_FUNC_INT1, LSM6DSO32_EMBEDDED_FUNC_BANK, LSM6DSO32_FSM_INT1_A, LSM6DSO32_FSM_INT1_B, LSM6DSO32_INT1_CTRL, LSM6DSO32_MD1_CFG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_USER_BANK, and lsm6dso32_pin_int1_route_t::md1_cfg.

Referenced by lsm6dso32_pin_int2_route_set().

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lsm6dso32_pin_int1_route_set()

int32_t lsm6dso32_pin_int1_route_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_pin_int1_route_t *	val
	)

Select the signal that need to route on int1 pad.[set].

Parameters

ctx	read / write interface definitions
val	struct of registers: INT1_CTRL, MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3113 of file lsm6dso32_reg.c.

{
  lsm6dso32_pin_int2_route_t pin_int2_route;
  lsm6dso32_tap_cfg2_t tap_cfg2;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
                              (uint8_t *)&val->emb_func_int1, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_A,
                              (uint8_t *)&val->fsm_int1_a, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_B,
                              (uint8_t *)&val->fsm_int1_b, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  if (ret == 0)
  {
    if ((val->emb_func_int1.int1_fsm_lc
         | val->emb_func_int1.int1_sig_mot
         | val->emb_func_int1.int1_step_detector
         | val->emb_func_int1.int1_tilt
         | val->fsm_int1_a.int1_fsm1
         | val->fsm_int1_a.int1_fsm2
         | val->fsm_int1_a.int1_fsm3
         | val->fsm_int1_a.int1_fsm4
         | val->fsm_int1_a.int1_fsm5
         | val->fsm_int1_a.int1_fsm6
         | val->fsm_int1_a.int1_fsm7
         | val->fsm_int1_a.int1_fsm8
         | val->fsm_int1_b.int1_fsm9
         | val->fsm_int1_b.int1_fsm10
         | val->fsm_int1_b.int1_fsm11
         | val->fsm_int1_b.int1_fsm12
         | val->fsm_int1_b.int1_fsm13
         | val->fsm_int1_b.int1_fsm14
         | val->fsm_int1_b.int1_fsm15
         | val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
    {
      val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
    }
 
    else
    {
      val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
    }
 
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT1_CTRL,
                              (uint8_t *)&val->int1_ctrl, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD1_CFG,
                              (uint8_t *)&val->md1_cfg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
                             (uint8_t *) &tap_cfg2, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_pin_int2_route_get(ctx, &pin_int2_route);
  }
 
  if (ret == 0)
  {
    if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
         | pin_int2_route.int2_ctrl.int2_drdy_g
         | pin_int2_route.int2_ctrl.int2_drdy_temp
         | pin_int2_route.int2_ctrl.int2_drdy_xl
         | pin_int2_route.int2_ctrl.int2_fifo_full
         | pin_int2_route.int2_ctrl.int2_fifo_ovr
         | pin_int2_route.int2_ctrl.int2_fifo_th
         | pin_int2_route.md2_cfg.int2_6d
         | pin_int2_route.md2_cfg.int2_double_tap
         | pin_int2_route.md2_cfg.int2_ff
         | pin_int2_route.md2_cfg.int2_wu
         | pin_int2_route.md2_cfg.int2_single_tap
         | pin_int2_route.md2_cfg.int2_sleep_change
         | val->int1_ctrl.den_drdy_flag
         | val->int1_ctrl.int1_boot
         | val->int1_ctrl.int1_cnt_bdr
         | val->int1_ctrl.int1_drdy_g
         | val->int1_ctrl.int1_drdy_xl
         | val->int1_ctrl.int1_fifo_full
         | val->int1_ctrl.int1_fifo_ovr
         | val->int1_ctrl.int1_fifo_th
         | val->md1_cfg.int1_6d
         | val->md1_cfg.int1_double_tap
         | val->md1_cfg.int1_ff
         | val->md1_cfg.int1_wu
         | val->md1_cfg.int1_single_tap
         | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
    {
      tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
    }
 
    else
    {
      tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
    }
 
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
                              (uint8_t *) &tap_cfg2, 1);
  }
 
  return ret;
}

References lsm6dso32_int1_ctrl_t::den_drdy_flag, lsm6dso32_pin_int1_route_t::emb_func_int1, lsm6dso32_pin_int1_route_t::fsm_int1_a, lsm6dso32_pin_int1_route_t::fsm_int1_b, lsm6dso32_md1_cfg_t::int1_6d, lsm6dso32_int1_ctrl_t::int1_boot, lsm6dso32_int1_ctrl_t::int1_cnt_bdr, lsm6dso32_pin_int1_route_t::int1_ctrl, lsm6dso32_md1_cfg_t::int1_double_tap, lsm6dso32_int1_ctrl_t::int1_drdy_g, lsm6dso32_int1_ctrl_t::int1_drdy_xl, lsm6dso32_md1_cfg_t::int1_emb_func, lsm6dso32_md1_cfg_t::int1_ff, lsm6dso32_int1_ctrl_t::int1_fifo_full, lsm6dso32_int1_ctrl_t::int1_fifo_ovr, lsm6dso32_int1_ctrl_t::int1_fifo_th, lsm6dso32_fsm_int1_a_t::int1_fsm1, lsm6dso32_fsm_int1_b_t::int1_fsm10, lsm6dso32_fsm_int1_b_t::int1_fsm11, lsm6dso32_fsm_int1_b_t::int1_fsm12, lsm6dso32_fsm_int1_b_t::int1_fsm13, lsm6dso32_fsm_int1_b_t::int1_fsm14, lsm6dso32_fsm_int1_b_t::int1_fsm15, lsm6dso32_fsm_int1_b_t::int1_fsm16, lsm6dso32_fsm_int1_a_t::int1_fsm2, lsm6dso32_fsm_int1_a_t::int1_fsm3, lsm6dso32_fsm_int1_a_t::int1_fsm4, lsm6dso32_fsm_int1_a_t::int1_fsm5, lsm6dso32_fsm_int1_a_t::int1_fsm6, lsm6dso32_fsm_int1_a_t::int1_fsm7, lsm6dso32_fsm_int1_a_t::int1_fsm8, lsm6dso32_fsm_int1_b_t::int1_fsm9, lsm6dso32_emb_func_int1_t::int1_fsm_lc, lsm6dso32_emb_func_int1_t::int1_sig_mot, lsm6dso32_md1_cfg_t::int1_single_tap, lsm6dso32_md1_cfg_t::int1_sleep_change, lsm6dso32_emb_func_int1_t::int1_step_detector, lsm6dso32_emb_func_int1_t::int1_tilt, lsm6dso32_md1_cfg_t::int1_wu, lsm6dso32_md2_cfg_t::int2_6d, lsm6dso32_int2_ctrl_t::int2_cnt_bdr, lsm6dso32_pin_int2_route_t::int2_ctrl, lsm6dso32_md2_cfg_t::int2_double_tap, lsm6dso32_int2_ctrl_t::int2_drdy_g, lsm6dso32_int2_ctrl_t::int2_drdy_temp, lsm6dso32_int2_ctrl_t::int2_drdy_xl, lsm6dso32_md2_cfg_t::int2_ff, lsm6dso32_int2_ctrl_t::int2_fifo_full, lsm6dso32_int2_ctrl_t::int2_fifo_ovr, lsm6dso32_int2_ctrl_t::int2_fifo_th, lsm6dso32_md2_cfg_t::int2_single_tap, lsm6dso32_md2_cfg_t::int2_sleep_change, lsm6dso32_md2_cfg_t::int2_wu, lsm6dso32_tap_cfg2_t::interrupts_enable, LSM6DSO32_EMB_FUNC_INT1, LSM6DSO32_EMBEDDED_FUNC_BANK, LSM6DSO32_FSM_INT1_A, LSM6DSO32_FSM_INT1_B, LSM6DSO32_INT1_CTRL, LSM6DSO32_MD1_CFG, lsm6dso32_mem_bank_set(), lsm6dso32_pin_int2_route_get(), lsm6dso32_read_reg(), LSM6DSO32_TAP_CFG2, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_pin_int1_route_t::md1_cfg, lsm6dso32_pin_int2_route_t::md2_cfg, PROPERTY_DISABLE, and PROPERTY_ENABLE.

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lsm6dso32_pin_int2_route_get()

int32_t lsm6dso32_pin_int2_route_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_pin_int2_route_t *	val
	)

Select the signal that need to route on int2 pad.[get].

Parameters

ctx	read / write interface definitions
val	union of registers INT2_CTRL, MD2_CFG, EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3443 of file lsm6dso32_reg.c.

{
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
                             (uint8_t *)&val->emb_func_int2, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_A,
                             (uint8_t *)&val->fsm_int2_a, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_B,
                             (uint8_t *)&val->fsm_int2_b, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT2_CTRL,
                             (uint8_t *)&val->int2_ctrl, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD2_CFG,
                             (uint8_t *)&val->md2_cfg, 1);
  }
 
  return ret;
}

References lsm6dso32_pin_int2_route_t::emb_func_int2, lsm6dso32_pin_int2_route_t::fsm_int2_a, lsm6dso32_pin_int2_route_t::fsm_int2_b, lsm6dso32_pin_int2_route_t::int2_ctrl, LSM6DSO32_EMB_FUNC_INT2, LSM6DSO32_EMBEDDED_FUNC_BANK, LSM6DSO32_FSM_INT2_A, LSM6DSO32_FSM_INT2_B, LSM6DSO32_INT2_CTRL, LSM6DSO32_MD2_CFG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_USER_BANK, and lsm6dso32_pin_int2_route_t::md2_cfg.

Referenced by lsm6dso32_pin_int1_route_set().

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lsm6dso32_pin_int2_route_set()

int32_t lsm6dso32_pin_int2_route_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_pin_int2_route_t *	val
	)

Select the signal that need to route on int2 pad.[set].

Parameters

ctx	read / write interface definitions
val	union of registers INT2_CTRL, MD2_CFG, EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3305 of file lsm6dso32_reg.c.

{
  lsm6dso32_pin_int1_route_t pin_int1_route;
  lsm6dso32_tap_cfg2_t tap_cfg2;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
                              (uint8_t *)&val->emb_func_int2, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_A,
                              (uint8_t *)&val->fsm_int2_a, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_B,
                              (uint8_t *)&val->fsm_int2_b, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  if (ret == 0)
  {
    if ((val->emb_func_int2.int2_fsm_lc
         | val->emb_func_int2.int2_sig_mot
         | val->emb_func_int2.int2_step_detector
         | val->emb_func_int2.int2_tilt
         | val->fsm_int2_a.int2_fsm1
         | val->fsm_int2_a.int2_fsm2
         | val->fsm_int2_a.int2_fsm3
         | val->fsm_int2_a.int2_fsm4
         | val->fsm_int2_a.int2_fsm5
         | val->fsm_int2_a.int2_fsm6
         | val->fsm_int2_a.int2_fsm7
         | val->fsm_int2_a.int2_fsm8
         | val->fsm_int2_b.int2_fsm9
         | val->fsm_int2_b.int2_fsm10
         | val->fsm_int2_b.int2_fsm11
         | val->fsm_int2_b.int2_fsm12
         | val->fsm_int2_b.int2_fsm13
         | val->fsm_int2_b.int2_fsm14
         | val->fsm_int2_b.int2_fsm15
         | val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
    {
      val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
    }
 
    else
    {
      val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
    }
 
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT2_CTRL,
                              (uint8_t *)&val->int2_ctrl, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD2_CFG,
                              (uint8_t *)&val->md2_cfg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
                             (uint8_t *) &tap_cfg2, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_pin_int1_route_get(ctx, &pin_int1_route);
  }
 
  if (ret == 0)
  {
    if ((val->int2_ctrl.int2_cnt_bdr
         | val->int2_ctrl.int2_drdy_g
         | val->int2_ctrl.int2_drdy_temp
         | val->int2_ctrl.int2_drdy_xl
         | val->int2_ctrl.int2_fifo_full
         | val->int2_ctrl.int2_fifo_ovr
         | val->int2_ctrl.int2_fifo_th
         | val->md2_cfg.int2_6d
         | val->md2_cfg.int2_double_tap
         | val->md2_cfg.int2_ff
         | val->md2_cfg.int2_wu
         | val->md2_cfg.int2_single_tap
         | val->md2_cfg.int2_sleep_change
         | pin_int1_route.int1_ctrl.den_drdy_flag
         | pin_int1_route.int1_ctrl.int1_boot
         | pin_int1_route.int1_ctrl.int1_cnt_bdr
         | pin_int1_route.int1_ctrl.int1_drdy_g
         | pin_int1_route.int1_ctrl.int1_drdy_xl
         | pin_int1_route.int1_ctrl.int1_fifo_full
         | pin_int1_route.int1_ctrl.int1_fifo_ovr
         | pin_int1_route.int1_ctrl.int1_fifo_th
         | pin_int1_route.md1_cfg.int1_6d
         | pin_int1_route.md1_cfg.int1_double_tap
         | pin_int1_route.md1_cfg.int1_ff
         | pin_int1_route.md1_cfg.int1_wu
         | pin_int1_route.md1_cfg.int1_single_tap
         | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
    {
      tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
    }
 
    else
    {
      tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
    }
 
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
                              (uint8_t *) &tap_cfg2, 1);
  }
 
  return ret;
}

References lsm6dso32_int1_ctrl_t::den_drdy_flag, lsm6dso32_pin_int2_route_t::emb_func_int2, lsm6dso32_pin_int2_route_t::fsm_int2_a, lsm6dso32_pin_int2_route_t::fsm_int2_b, lsm6dso32_md1_cfg_t::int1_6d, lsm6dso32_int1_ctrl_t::int1_boot, lsm6dso32_int1_ctrl_t::int1_cnt_bdr, lsm6dso32_pin_int1_route_t::int1_ctrl, lsm6dso32_md1_cfg_t::int1_double_tap, lsm6dso32_int1_ctrl_t::int1_drdy_g, lsm6dso32_int1_ctrl_t::int1_drdy_xl, lsm6dso32_md1_cfg_t::int1_ff, lsm6dso32_int1_ctrl_t::int1_fifo_full, lsm6dso32_int1_ctrl_t::int1_fifo_ovr, lsm6dso32_int1_ctrl_t::int1_fifo_th, lsm6dso32_md1_cfg_t::int1_single_tap, lsm6dso32_md1_cfg_t::int1_sleep_change, lsm6dso32_md1_cfg_t::int1_wu, lsm6dso32_md2_cfg_t::int2_6d, lsm6dso32_int2_ctrl_t::int2_cnt_bdr, lsm6dso32_pin_int2_route_t::int2_ctrl, lsm6dso32_md2_cfg_t::int2_double_tap, lsm6dso32_int2_ctrl_t::int2_drdy_g, lsm6dso32_int2_ctrl_t::int2_drdy_temp, lsm6dso32_int2_ctrl_t::int2_drdy_xl, lsm6dso32_md2_cfg_t::int2_emb_func, lsm6dso32_md2_cfg_t::int2_ff, lsm6dso32_int2_ctrl_t::int2_fifo_full, lsm6dso32_int2_ctrl_t::int2_fifo_ovr, lsm6dso32_int2_ctrl_t::int2_fifo_th, lsm6dso32_fsm_int2_a_t::int2_fsm1, lsm6dso32_fsm_int2_b_t::int2_fsm10, lsm6dso32_fsm_int2_b_t::int2_fsm11, lsm6dso32_fsm_int2_b_t::int2_fsm12, lsm6dso32_fsm_int2_b_t::int2_fsm13, lsm6dso32_fsm_int2_b_t::int2_fsm14, lsm6dso32_fsm_int2_b_t::int2_fsm15, lsm6dso32_fsm_int2_b_t::int2_fsm16, lsm6dso32_fsm_int2_a_t::int2_fsm2, lsm6dso32_fsm_int2_a_t::int2_fsm3, lsm6dso32_fsm_int2_a_t::int2_fsm4, lsm6dso32_fsm_int2_a_t::int2_fsm5, lsm6dso32_fsm_int2_a_t::int2_fsm6, lsm6dso32_fsm_int2_a_t::int2_fsm7, lsm6dso32_fsm_int2_a_t::int2_fsm8, lsm6dso32_fsm_int2_b_t::int2_fsm9, lsm6dso32_emb_func_int2_t::int2_fsm_lc, lsm6dso32_emb_func_int2_t::int2_sig_mot, lsm6dso32_md2_cfg_t::int2_single_tap, lsm6dso32_md2_cfg_t::int2_sleep_change, lsm6dso32_emb_func_int2_t::int2_step_detector, lsm6dso32_emb_func_int2_t::int2_tilt, lsm6dso32_md2_cfg_t::int2_wu, lsm6dso32_tap_cfg2_t::interrupts_enable, LSM6DSO32_EMB_FUNC_INT2, LSM6DSO32_EMBEDDED_FUNC_BANK, LSM6DSO32_FSM_INT2_A, LSM6DSO32_FSM_INT2_B, LSM6DSO32_INT2_CTRL, LSM6DSO32_MD2_CFG, lsm6dso32_mem_bank_set(), lsm6dso32_pin_int1_route_get(), lsm6dso32_read_reg(), LSM6DSO32_TAP_CFG2, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_pin_int1_route_t::md1_cfg, lsm6dso32_pin_int2_route_t::md2_cfg, PROPERTY_DISABLE, and PROPERTY_ENABLE.

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lsm6dso32_pin_mode_get()

int32_t lsm6dso32_pin_mode_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_pp_od_t *	val
	)

Push-pull/open drain selection on interrupt pads.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of pp_od in reg CTRL3_C

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3521 of file lsm6dso32_reg.c.

{
  lsm6dso32_ctrl3_c_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)&reg, 1);
 
  switch (reg.pp_od)
  {
    case LSM6DSO32_PUSH_PULL:
      *val = LSM6DSO32_PUSH_PULL;
      break;
 
    case LSM6DSO32_OPEN_DRAIN:
      *val = LSM6DSO32_OPEN_DRAIN;
      break;
 
    default:
      *val = LSM6DSO32_PUSH_PULL;
      break;
  }
 
  return ret;
}

References LSM6DSO32_CTRL3_C, LSM6DSO32_OPEN_DRAIN, LSM6DSO32_PUSH_PULL, lsm6dso32_read_reg(), and lsm6dso32_ctrl3_c_t::pp_od.

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lsm6dso32_pin_mode_set()

int32_t lsm6dso32_pin_mode_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_pp_od_t	val
	)

Push-pull/open drain selection on interrupt pads.[set].

Parameters

ctx	read / write interface definitions
val	change the values of pp_od in reg CTRL3_C

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3496 of file lsm6dso32_reg.c.

{
  lsm6dso32_ctrl3_c_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.pp_od = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}

References LSM6DSO32_CTRL3_C, lsm6dso32_read_reg(), lsm6dso32_write_reg(), and lsm6dso32_ctrl3_c_t::pp_od.

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lsm6dso32_pin_polarity_get()

int32_t lsm6dso32_pin_polarity_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_h_lactive_t *	val
	)

Interrupt active-high/low.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of h_lactive in reg CTRL3_C

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3580 of file lsm6dso32_reg.c.

{
  lsm6dso32_ctrl3_c_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)&reg, 1);
 
  switch (reg.h_lactive)
  {
    case LSM6DSO32_ACTIVE_HIGH:
      *val = LSM6DSO32_ACTIVE_HIGH;
      break;
 
    case LSM6DSO32_ACTIVE_LOW:
      *val = LSM6DSO32_ACTIVE_LOW;
      break;
 
    default:
      *val = LSM6DSO32_ACTIVE_HIGH;
      break;
  }
 
  return ret;
}

References lsm6dso32_ctrl3_c_t::h_lactive, LSM6DSO32_ACTIVE_HIGH, LSM6DSO32_ACTIVE_LOW, LSM6DSO32_CTRL3_C, and lsm6dso32_read_reg().

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lsm6dso32_pin_polarity_set()

int32_t lsm6dso32_pin_polarity_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_h_lactive_t	val
	)

Interrupt active-high/low.[set].

Parameters

ctx	read / write interface definitions
val	change the values of h_lactive in reg CTRL3_C

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 3555 of file lsm6dso32_reg.c.

{
  lsm6dso32_ctrl3_c_t reg;
  int32_t ret;
 
  ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.h_lactive = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}

References lsm6dso32_ctrl3_c_t::h_lactive, LSM6DSO32_CTRL3_C, lsm6dso32_read_reg(), and lsm6dso32_write_reg().

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