lis2mdl_reg.c

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#include "lis2mdl_reg.h"
#include "main.h"
 
#ifndef LIS2MDL_CS_GPIO_Port
#define LIS2MDL_CS_GPIO_Port  MAG_CS_GPIO_Port // Example GPIO Port
#endif
#ifndef LIS2MDL_CS_Pin
#define LIS2MDL_CS_Pin        MAG_CS_Pin // Example GPIO Pin
#endif
 
// Placeholder for HAL_Delay function (usually available)
#ifndef platform_delay
#define platform_delay(ms) HAL_Delay(ms)
#endif
 
// SPI timeout duration in milliseconds
#define LIS2MDL_SPI_TIMEOUT 100
 
int32_t __weak lis2mdl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
                                uint8_t *data,
                                uint16_t len)
{
  int32_t ret;
 
  if (ctx == NULL)
  {
    return -1;
  }
 
  ret = ctx->read_reg(ctx->handle, reg, data, len);
 
  return ret;
}
 
int32_t __weak lis2mdl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
                                 uint8_t *data,
                                 uint16_t len)
{
  int32_t ret;
 
  if (ctx == NULL)
  {
    return -1;
  }
 
  ret = ctx->write_reg(ctx->handle, reg, data, len);
 
  return ret;
}
 
float_t lis2mdl_from_lsb_to_mgauss(int16_t lsb)
{
  return ((float_t)lsb * 1.5f);
}
 
float_t lis2mdl_from_lsb_to_celsius(int16_t lsb)
{
  return (((float_t)lsb / 8.0f) + 25.0f);
}
 
float_t lis2mdl_from_lsb_to_nanotesla(int16_t lsb)
{
  return ((float_t)lsb * 150.0f);
}
 
int32_t lis2mdl_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
{
  uint8_t buff[6];
  int32_t ret;
 
  buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
  buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
  buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
  buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
  buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
  buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
  ret = lis2mdl_write_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
 
  return ret;
}
 
int32_t lis2mdl_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
{
  uint8_t buff[6];
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
  val[0] = (int16_t)buff[1];
  val[0] = (val[0] * 256) + (int16_t)buff[0];
  val[1] = (int16_t)buff[3];
  val[1] = (val[1] * 256) + (int16_t)buff[2];
  val[2] = (int16_t)buff[5];
  val[2] = (val[2] * 256) + (int16_t)buff[4];
 
  return ret;
}
 
int32_t lis2mdl_operating_mode_set(const stmdev_ctx_t *ctx,
                                   lis2mdl_md_t val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.md = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_operating_mode_get(const stmdev_ctx_t *ctx,
                                   lis2mdl_md_t *val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  switch (reg.md)
  {
    case LIS2MDL_POWER_DOWN:
      *val = LIS2MDL_POWER_DOWN;
      break;
 
    case LIS2MDL_CONTINUOUS_MODE:
      *val = LIS2MDL_CONTINUOUS_MODE;
      break;
 
    case LIS2MDL_SINGLE_TRIGGER:
      *val = LIS2MDL_SINGLE_TRIGGER;
      break;
 
    default:
      *val = LIS2MDL_POWER_DOWN;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_data_rate_set(const stmdev_ctx_t *ctx, lis2mdl_odr_t val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.odr = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_data_rate_get(const stmdev_ctx_t *ctx, lis2mdl_odr_t *val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  switch (reg.odr)
  {
    case LIS2MDL_ODR_10Hz:
      *val = LIS2MDL_ODR_10Hz;
      break;
 
    case LIS2MDL_ODR_20Hz:
      *val = LIS2MDL_ODR_20Hz;
      break;
 
    case LIS2MDL_ODR_50Hz:
      *val = LIS2MDL_ODR_50Hz;
      break;
 
    case LIS2MDL_ODR_100Hz:
      *val = LIS2MDL_ODR_100Hz;
      break;
 
    default:
      *val = LIS2MDL_ODR_10Hz;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_power_mode_set(const stmdev_ctx_t *ctx, lis2mdl_lp_t val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.lp = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_power_mode_get(const stmdev_ctx_t *ctx, lis2mdl_lp_t *val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  switch (reg.lp)
  {
    case LIS2MDL_HIGH_RESOLUTION:
      *val = LIS2MDL_HIGH_RESOLUTION;
      break;
 
    case LIS2MDL_LOW_POWER:
      *val = LIS2MDL_LOW_POWER;
      break;
 
    default:
      *val = LIS2MDL_HIGH_RESOLUTION;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.comp_temp_en = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  *val = reg.comp_temp_en;
 
  return ret;
}
 
int32_t lis2mdl_low_pass_bandwidth_set(const stmdev_ctx_t *ctx,
                                       lis2mdl_lpf_t val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.lpf = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_low_pass_bandwidth_get(const stmdev_ctx_t *ctx,
                                       lis2mdl_lpf_t *val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  switch (reg.lpf)
  {
    case LIS2MDL_ODR_DIV_2:
      *val = LIS2MDL_ODR_DIV_2;
      break;
 
    case LIS2MDL_ODR_DIV_4:
      *val = LIS2MDL_ODR_DIV_4;
      break;
 
    default:
      *val = LIS2MDL_ODR_DIV_2;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_set_rst_mode_set(const stmdev_ctx_t *ctx,
                                 lis2mdl_set_rst_t val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.set_rst = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_set_rst_mode_get(const stmdev_ctx_t *ctx,
                                 lis2mdl_set_rst_t *val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  switch (reg.set_rst)
  {
    case LIS2MDL_SET_SENS_ODR_DIV_63:
      *val = LIS2MDL_SET_SENS_ODR_DIV_63;
      break;
 
    case LIS2MDL_SENS_OFF_CANC_EVERY_ODR:
      *val = LIS2MDL_SENS_OFF_CANC_EVERY_ODR;
      break;
 
    case LIS2MDL_SET_SENS_ONLY_AT_POWER_ON:
      *val = LIS2MDL_SET_SENS_ONLY_AT_POWER_ON;
      break;
 
    default:
      *val = LIS2MDL_SET_SENS_ODR_DIV_63;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_set_rst_sensor_single_set(const stmdev_ctx_t *ctx,
                                          uint8_t val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.off_canc_one_shot = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_set_rst_sensor_single_get(const stmdev_ctx_t *ctx,
                                          uint8_t *val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
  *val = reg.off_canc_one_shot;
 
  return ret;
}
 
int32_t lis2mdl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.bdu = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  *val = reg.bdu;
 
  return ret;
}
 
int32_t lis2mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_status_reg_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)&reg, 1);
  *val = reg.zyxda;
 
  return ret;
}
 
int32_t lis2mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_status_reg_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)&reg, 1);
  *val = reg.zyxor;
 
  return ret;
}
 
int32_t lis2mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
  uint8_t buff[6];
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_OUTX_L_REG, buff, 6);
  val[0] = (int16_t)buff[1];
  val[0] = (val[0] * 256) + (int16_t)buff[0];
  val[1] = (int16_t)buff[3];
  val[1] = (val[1] * 256) + (int16_t)buff[2];
  val[2] = (int16_t)buff[5];
  val[2] = (val[2] * 256) + (int16_t)buff[4];
 
  return ret;
}
 
int32_t lis2mdl_temperature_raw_get(const stmdev_ctx_t *ctx,  int16_t *val)
{
  uint8_t buff[2];
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_TEMP_OUT_L_REG, buff, 2);
  *val = (int16_t)buff[1];
  *val = (*val * 256) + (int16_t)buff[0];
 
  return ret;
}
 
int32_t lis2mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
{
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_WHO_AM_I, buff, 1);
 
  return ret;
}
 
int32_t lis2mdl_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.soft_rst = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  *val = reg.soft_rst;
 
  return ret;
}
 
int32_t lis2mdl_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.reboot = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_a_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)&reg, 1);
  *val = reg.reboot;
 
  return ret;
}
 
int32_t lis2mdl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.self_test = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  *val = reg.self_test;
 
  return ret;
}
 
int32_t lis2mdl_data_format_set(const stmdev_ctx_t *ctx, lis2mdl_ble_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.ble = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_data_format_get(const stmdev_ctx_t *ctx, lis2mdl_ble_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  switch (reg.ble)
  {
    case LIS2MDL_LSB_AT_LOW_ADD:
      *val = LIS2MDL_LSB_AT_LOW_ADD;
      break;
 
    case LIS2MDL_MSB_AT_LOW_ADD:
      *val = LIS2MDL_MSB_AT_LOW_ADD;
      break;
 
    default:
      *val = LIS2MDL_LSB_AT_LOW_ADD;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_status_get(const stmdev_ctx_t *ctx,
                           lis2mdl_status_reg_t *val)
{
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t lis2mdl_offset_int_conf_set(const stmdev_ctx_t *ctx,
                                    lis2mdl_int_on_dataoff_t val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.int_on_dataoff = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_offset_int_conf_get(const stmdev_ctx_t *ctx,
                                    lis2mdl_int_on_dataoff_t *val)
{
  lis2mdl_cfg_reg_b_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)&reg, 1);
 
  switch (reg.int_on_dataoff)
  {
    case LIS2MDL_CHECK_BEFORE:
      *val = LIS2MDL_CHECK_BEFORE;
      break;
 
    case LIS2MDL_CHECK_AFTER:
      *val = LIS2MDL_CHECK_AFTER;
      break;
 
    default:
      *val = LIS2MDL_CHECK_BEFORE;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.drdy_on_pin = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  *val = reg.drdy_on_pin;
 
  return ret;
}
 
int32_t lis2mdl_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.int_on_pin = val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  *val = reg.int_on_pin;
 
  return ret;
}
 
int32_t lis2mdl_int_gen_conf_set(const stmdev_ctx_t *ctx,
                                 lis2mdl_int_crtl_reg_t *val)
{
  int32_t ret;
 
  ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t lis2mdl_int_gen_conf_get(const stmdev_ctx_t *ctx,
                                 lis2mdl_int_crtl_reg_t *val)
{
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t lis2mdl_int_gen_source_get(const stmdev_ctx_t *ctx,
                                   lis2mdl_int_source_reg_t *val)
{
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_SOURCE_REG, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t lis2mdl_int_gen_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
{
  uint8_t buff[2];
  int32_t ret;
 
  buff[1] = (uint8_t)(val / 256U);
  buff[0] = (uint8_t)(val - (buff[1] * 256U));
  ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
 
  return ret;
}
 
int32_t lis2mdl_int_gen_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
{
  uint8_t buff[2];
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
  *val = buff[1];
  *val = (*val * 256U) +  buff[0];
 
  return ret;
}
 
int32_t lis2mdl_spi_mode_set(const stmdev_ctx_t *ctx, lis2mdl_sim_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg._4wspi = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis2mdl_sim_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  switch (reg._4wspi)
  {
    case LIS2MDL_SPI_4_WIRE:
      *val = LIS2MDL_SPI_4_WIRE;
      break;
 
    case LIS2MDL_SPI_3_WIRE:
      *val = LIS2MDL_SPI_3_WIRE;
      break;
 
    default:
      *val = LIS2MDL_SPI_3_WIRE;
      break;
  }
 
  return ret;
}
 
int32_t lis2mdl_i2c_interface_set(const stmdev_ctx_t *ctx,
                                  lis2mdl_i2c_dis_t val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  if (ret == 0)
  {
    reg.i2c_dis = (uint8_t)val;
    ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
  }
 
  return ret;
}
 
int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx,
                                  lis2mdl_i2c_dis_t *val)
{
  lis2mdl_cfg_reg_c_t reg;
  int32_t ret;
 
  ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)&reg, 1);
 
  switch (reg.i2c_dis)
  {
    case LIS2MDL_I2C_ENABLE:
      *val = LIS2MDL_I2C_ENABLE;
      break;
 
    case LIS2MDL_I2C_DISABLE:
      *val = LIS2MDL_I2C_DISABLE;
      break;
 
    default:
      *val = LIS2MDL_I2C_ENABLE;
      break;
  }
 
  return ret;
}
 
static int32_t platform_spi_write(void *handle, uint8_t reg, const uint8_t *bufp, uint16_t len)
{
  SPI_HandleTypeDef *spi_handle = (SPI_HandleTypeDef *)handle;
  uint8_t cmd_byte;
 
  if (spi_handle == NULL || bufp == NULL) {
    return -1; // Invalid arguments
  }
 
  // LIS2MDL SPI write command: MSB=0 for write, followed by 7-bit register address
  cmd_byte = reg & 0x7F; // Ensure MSB is 0 for write
 
  BMP390_CS_HIGH;
  IMU_CS_HIGH;
  // Pull CS pin low to select the device
  HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_RESET);
 
 
  // Transmit the command byte (register address with write flag)
  if (HAL_SPI_Transmit(spi_handle, &cmd_byte, 1, LIS2MDL_SPI_TIMEOUT) != HAL_OK)
  {
    HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_SET); // Release CS
    return -1; // SPI transmission error
  }
 
  // Transmit the data
  if (HAL_SPI_Transmit(spi_handle, (uint8_t*)bufp, len, LIS2MDL_SPI_TIMEOUT) != HAL_OK)
  {
    HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_SET); // Release CS
    return -1; // SPI transmission error
  }
 
  // Pull CS pin high to deselect the device
  HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_SET);
 
  return 0; // Success
}
 
static int32_t platform_spi_read(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len)
{
  SPI_HandleTypeDef *spi_handle = (SPI_HandleTypeDef *)handle;
  uint8_t cmd_byte;
 
  if (spi_handle == NULL || bufp == NULL) {
    return -1; // Invalid arguments
  }
 
  // LIS2MDL SPI read command: MSB=1 for read, followed by 7-bit register address
  cmd_byte = (reg & 0x7F) | 0x80; // Set MSB to 1 for read
 
 
  if(HAL_GPIO_ReadPin(IMU_CS_GPIO_Port,IMU_CS_Pin)!=GPIO_PIN_SET){IMU_CS_HIGH;}
  if(HAL_GPIO_ReadPin(BARO_CS_GPIO_Port,BARO_CS_Pin)!=GPIO_PIN_SET){BMP390_CS_HIGH;}
  // Pull CS pin low to select the device
  HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_RESET);
 
  // Transmit the command byte (register address with read flag)
  if (HAL_SPI_Transmit(spi_handle, &cmd_byte, 1, LIS2MDL_SPI_TIMEOUT) != HAL_OK)
  {
    HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_SET); // Release CS
    return -1; // SPI transmission error
  }
 
  // Receive the data
  if (HAL_SPI_Receive(spi_handle, bufp, len, LIS2MDL_SPI_TIMEOUT) != HAL_OK)
  {
    HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_SET); // Release CS
    return -1; // SPI reception error
  }
 
  // Pull CS pin high to deselect the device
  HAL_GPIO_WritePin(LIS2MDL_CS_GPIO_Port, LIS2MDL_CS_Pin, GPIO_PIN_SET);
 
  return 0; // Success
}
 
int32_t lis2mdl_init(stmdev_ctx_t *ctx)
{
  uint8_t who_am_i = 0;
  uint8_t val = 0; // Temporary variable for get functions
  lis2mdl_cfg_reg_a_t cfg_a;
  lis2mdl_cfg_reg_c_t cfg_c;
 
 
  if (ctx == NULL) return -1;
 
 
  ctx->write_reg = platform_spi_write;
  ctx->read_reg = platform_spi_read;
  ctx->handle = &hspi2; // Your SPI_HandleTypeDef
 
  // Check WHO_AM_I register
  if (lis2mdl_device_id_get(ctx, &who_am_i) != 0) return -1; // Error reading WHO_AM_I
  if (who_am_i != LIS2MDL_ID){
      return -1;
  }  // WHO_AM_I mismatch (LIS2MDL_ID should be 0x40 as per datasheet)
 
  // Perform a software reset
  if (lis2mdl_reset_set(ctx, 1) != 0) return -1;
  platform_delay(5); // Wait for reset to complete (datasheet doesn't specify, 5ms is a guess)
  do {
    if (lis2mdl_reset_get(ctx, &val) != 0) return -1;
  } while (val); // Poll SOFT_RST bit until it is cleared
 
 
  // Reboot memory content to reload calibration parameters
  if (lis2mdl_boot_set(ctx, 1) != 0) return -1;
  platform_delay(5); // Wait for boot to complete
   do {
    if (lis2mdl_boot_get(ctx, &val) != 0) return -1;
  } while (val); // Poll REBOOT bit until it is cleared
 
  // Configure for 4-wire SPI mode
  // Note: The LIS2MDL CS pin (pin 3) must be tied LOW to enable SPI mode.
  // This function configures the 4WSPI bit in CFG_REG_C for the SDO line.
  if (lis2mdl_spi_mode_set(ctx, LIS2MDL_SPI_4_WIRE) != 0) return -1;
 
 
  // Configure CFG_REG_A for:
  // - Temperature compensation enabled
  // - Continuous mode
  // - ODR 10 Hz
  // - High-resolution mode
  // This matches the datasheet startup example (CFG_REG_A = 0x80)
 
  // Method 1: Using individual set functions (less efficient due to multiple R-M-W)
  // if (lis2mdl_offset_temp_comp_set(ctx, 1) != 0) return -1;
  // if (lis2mdl_operating_mode_set(ctx, LIS2MDL_CONTINUOUS_MODE) != 0) return -1;
  // if (lis2mdl_data_rate_set(ctx, LIS2MDL_ODR_10HZ) != 0) return -1; // Assuming LIS2MDL_ODR_10HZ is defined
  // if (lis2mdl_power_mode_set(ctx, LIS2MDL_HIGH_RESOLUTION) != 0) return -1;
 
  // Method 2: Direct write to CFG_REG_A (more efficient)
  cfg_a.comp_temp_en = 1;
  cfg_a.reboot = 0;
  cfg_a.soft_rst = 0;
  cfg_a.lp = (uint8_t)LIS2MDL_HIGH_RESOLUTION; // Assuming LIS2MDL_HIGH_RESOLUTION = 0
  cfg_a.odr = (uint8_t)LIS2MDL_ODR_10Hz;       // Assuming LIS2MDL_ODR_10Hz = 0
  cfg_a.md = (uint8_t)LIS2MDL_CONTINUOUS_MODE; // Assuming LIS2MDL_CONTINUOUS_MODE = 0
  if (lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)&cfg_a, 1) != 0) return -1;
 
 
  // Configure CFG_REG_C for:
  // - Block Data Update (BDU) enabled
  // - Data Ready signal on INT/DRDY pin enabled (optional, as per datasheet startup example)
  // - 4-wire SPI is already set by lis2mdl_spi_mode_set above.
 
  // Method 1: Using individual set functions
  // if (lis2mdl_block_data_update_set(ctx, 1) != 0) return -1;
  // if (lis2mdl_drdy_on_pin_set(ctx, 1) != 0) return -1; // Optional: enable DRDY on pin
 
  // Method 2: Direct write to CFG_REG_C (more efficient, considers 4WSPI already set)
  if (lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)&cfg_c, 1) != 0) return -1;
  cfg_c.bdu = 1;
  cfg_c.drdy_on_pin = 1; // Enable DRDY on pin as per datasheet example
  // cfg_c._4wspi is already set by lis2mdl_spi_mode_set, no need to change it here
  // unless lis2mdl_spi_mode_set is not called before this.
  // For safety, ensure it's set if not using the dedicated function earlier:
  // cfg_c._4wspi = 1; // If LIS2MDL_SPI_4_WIRE is desired
  cfg_c.i2c_dis = 1; // Disable I2C if exclusively using SPI
  cfg_c.int_on_pin = 0; // Disable interrupt on pin unless specifically needed
  cfg_c.self_test = 0; // Disable self-test
  cfg_c.ble = (uint8_t)LIS2MDL_LSB_AT_LOW_ADD; // Default data format
 
  if (lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)&cfg_c, 1) != 0) return -1;
 
 
  // Sensor is now initialized with basic settings.
  // Further configuration (e.g., interrupts, thresholds) can be done as needed.
  return 0; // Success
}
 
int32_t lis2mdl_init_2(stmdev_ctx_t *ctx)
{
  uint8_t who_am_i = 0;
  uint8_t val = 0; // Temporary variable for get functions
  lis2mdl_cfg_reg_a_t cfg_a;
  lis2mdl_cfg_reg_c_t cfg_c;
 
 
  if (ctx == NULL) return -1;
 
 
  ctx->write_reg = platform_spi_write;
  ctx->read_reg = platform_spi_read;
  ctx->handle = &hspi3; // Your SPI_HandleTypeDef
 
  // Check WHO_AM_I register
  if (lis2mdl_device_id_get(ctx, &who_am_i) != 0) return -1; // Error reading WHO_AM_I
  if (who_am_i != LIS2MDL_ID) return -1; // WHO_AM_I mismatch (LIS2MDL_ID should be 0x40 as per datasheet)
 
  // Perform a software reset
  if (lis2mdl_reset_set(ctx, 1) != 0) return -1;
  platform_delay(5); // Wait for reset to complete (datasheet doesn't specify, 5ms is a guess)
  do {
    if (lis2mdl_reset_get(ctx, &val) != 0) return -1;
  } while (val); // Poll SOFT_RST bit until it is cleared
 
 
  // Reboot memory content to reload calibration parameters
  if (lis2mdl_boot_set(ctx, 1) != 0) return -1;
  platform_delay(5); // Wait for boot to complete
   do {
    if (lis2mdl_boot_get(ctx, &val) != 0) return -1;
  } while (val); // Poll REBOOT bit until it is cleared
 
  // Configure for 4-wire SPI mode
  // Note: The LIS2MDL CS pin (pin 3) must be tied LOW to enable SPI mode.
  // This function configures the 4WSPI bit in CFG_REG_C for the SDO line.
  if (lis2mdl_spi_mode_set(ctx, LIS2MDL_SPI_4_WIRE) != 0) return -1;
 
 
  // Configure CFG_REG_A for:
  // - Temperature compensation enabled
  // - Continuous mode
  // - ODR 10 Hz
  // - High-resolution mode
  // This matches the datasheet startup example (CFG_REG_A = 0x80)
 
  // Method 1: Using individual set functions (less efficient due to multiple R-M-W)
  // if (lis2mdl_offset_temp_comp_set(ctx, 1) != 0) return -1;
  // if (lis2mdl_operating_mode_set(ctx, LIS2MDL_CONTINUOUS_MODE) != 0) return -1;
  // if (lis2mdl_data_rate_set(ctx, LIS2MDL_ODR_10HZ) != 0) return -1; // Assuming LIS2MDL_ODR_10HZ is defined
  // if (lis2mdl_power_mode_set(ctx, LIS2MDL_HIGH_RESOLUTION) != 0) return -1;
 
  // Method 2: Direct write to CFG_REG_A (more efficient)
  cfg_a.comp_temp_en = 1;
  cfg_a.reboot = 0;
  cfg_a.soft_rst = 0;
  cfg_a.lp = (uint8_t)LIS2MDL_HIGH_RESOLUTION; // Assuming LIS2MDL_HIGH_RESOLUTION = 0
  cfg_a.odr = (uint8_t)LIS2MDL_ODR_10Hz;       // Assuming LIS2MDL_ODR_10Hz = 0
  cfg_a.md = (uint8_t)LIS2MDL_CONTINUOUS_MODE; // Assuming LIS2MDL_CONTINUOUS_MODE = 0
  if (lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t*)&cfg_a, 1) != 0) return -1;
 
 
  // Configure CFG_REG_C for:
  // - Block Data Update (BDU) enabled
  // - Data Ready signal on INT/DRDY pin enabled (optional, as per datasheet startup example)
  // - 4-wire SPI is already set by lis2mdl_spi_mode_set above.
 
  // Method 1: Using individual set functions
  // if (lis2mdl_block_data_update_set(ctx, 1) != 0) return -1;
  // if (lis2mdl_drdy_on_pin_set(ctx, 1) != 0) return -1; // Optional: enable DRDY on pin
 
  // Method 2: Direct write to CFG_REG_C (more efficient, considers 4WSPI already set)
  if (lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)&cfg_c, 1) != 0) return -1;
  cfg_c.bdu = 1;
  cfg_c.drdy_on_pin = 1; // Enable DRDY on pin as per datasheet example
  // cfg_c._4wspi is already set by lis2mdl_spi_mode_set, no need to change it here
  // unless lis2mdl_spi_mode_set is not called before this.
  // For safety, ensure it's set if not using the dedicated function earlier:
  // cfg_c._4wspi = 1; // If LIS2MDL_SPI_4_WIRE is desired
  cfg_c.i2c_dis = 1; // Disable I2C if exclusively using SPI
  cfg_c.int_on_pin = 0; // Disable interrupt on pin unless specifically needed
  cfg_c.self_test = 0; // Disable self-test
  cfg_c.ble = (uint8_t)LIS2MDL_LSB_AT_LOW_ADD; // Default data format
 
  if (lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t*)&cfg_c, 1) != 0) return -1;
 
 
  // Sensor is now initialized with basic settings.
  // Further configuration (e.g., interrupts, thresholds) can be done as needed.
  return 0; // Success
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/