LSM6DSO32_Sensor_hub

This section groups all the functions that manage the sensor hub. More...

Collaboration diagram for LSM6DSO32_Sensor_hub:

Functions
int32_t	lsm6dso32_sh_read_data_raw_get (stmdev_ctx_t *ctx, lsm6dso32_emb_sh_read_t *val)
	Sensor hub output registers.[get].
int32_t	lsm6dso32_sh_slave_connected_set (stmdev_ctx_t *ctx, lsm6dso32_aux_sens_on_t val)
	Number of external sensors to be read by the sensor hub.[set].
int32_t	lsm6dso32_sh_slave_connected_get (stmdev_ctx_t *ctx, lsm6dso32_aux_sens_on_t *val)
	Number of external sensors to be read by the sensor hub.[get].
int32_t	lsm6dso32_sh_master_set (stmdev_ctx_t *ctx, uint8_t val)
	Sensor hub I2C master enable.[set].
int32_t	lsm6dso32_sh_master_get (stmdev_ctx_t *ctx, uint8_t *val)
	Sensor hub I2C master enable.[get].
int32_t	lsm6dso32_sh_pin_mode_set (stmdev_ctx_t *ctx, lsm6dso32_shub_pu_en_t val)
	Master I2C pull-up enable.[set].
int32_t	lsm6dso32_sh_pin_mode_get (stmdev_ctx_t *ctx, lsm6dso32_shub_pu_en_t *val)
	Master I2C pull-up enable.[get].
int32_t	lsm6dso32_sh_pass_through_set (stmdev_ctx_t *ctx, uint8_t val)
	I2C interface pass-through.[set].
int32_t	lsm6dso32_sh_pass_through_get (stmdev_ctx_t *ctx, uint8_t *val)
	I2C interface pass-through.[get].
int32_t	lsm6dso32_sh_syncro_mode_set (stmdev_ctx_t *ctx, lsm6dso32_start_config_t val)
	Sensor hub trigger signal selection.[set].
int32_t	lsm6dso32_sh_syncro_mode_get (stmdev_ctx_t *ctx, lsm6dso32_start_config_t *val)
	Sensor hub trigger signal selection.[get].
int32_t	lsm6dso32_sh_write_mode_set (stmdev_ctx_t *ctx, lsm6dso32_write_once_t val)
	Slave 0 write operation is performed only at the first sensor hub cycle.[set].
int32_t	lsm6dso32_sh_write_mode_get (stmdev_ctx_t *ctx, lsm6dso32_write_once_t *val)
	Slave 0 write operation is performed only at the first sensor hub cycle.[get].
int32_t	lsm6dso32_sh_reset_set (stmdev_ctx_t *ctx)
	Reset Master logic and output registers.[set].
int32_t	lsm6dso32_sh_reset_get (stmdev_ctx_t *ctx, uint8_t *val)
	Reset Master logic and output registers.[get].
int32_t	lsm6dso32_sh_data_rate_set (stmdev_ctx_t *ctx, lsm6dso32_shub_odr_t val)
	Rate at which the master communicates.[set].
int32_t	lsm6dso32_sh_data_rate_get (stmdev_ctx_t *ctx, lsm6dso32_shub_odr_t *val)
	Rate at which the master communicates.[get].
int32_t	lsm6dso32_sh_cfg_write (stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_write_t *val)
	Configure slave 0 for perform a write.[set].
int32_t	lsm6dso32_sh_slv0_cfg_read (stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val)
	Configure slave 0 for perform a read.[set].
int32_t	lsm6dso32_sh_slv1_cfg_read (stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val)
	Configure slave 0 for perform a write/read.[set].
int32_t	lsm6dso32_sh_slv2_cfg_read (stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val)
	Configure slave 0 for perform a write/read.[set].
int32_t	lsm6dso32_sh_slv3_cfg_read (stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val)
	Configure slave 0 for perform a write/read.[set].
int32_t	lsm6dso32_sh_status_get (stmdev_ctx_t *ctx, lsm6dso32_status_master_t *val)
	Sensor hub source register.[get].

Detailed Description

This section groups all the functions that manage the sensor hub.

Function Documentation

lsm6dso32_sh_cfg_write()

int32_t lsm6dso32_sh_cfg_write	(	stmdev_ctx_t *	ctx,
		lsm6dso32_sh_cfg_write_t *	val
	)

Configure slave 0 for perform a write.[set].

Parameters

ctx	read / write interface definitions
val	a structure that contain uint8_t slv1_add; 8 bit i2c device address uint8_t slv1_subadd; 8 bit register device address uint8_t slv1_data; 8 bit data to write

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9551 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv0_add_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    reg.slave0 = val->slv0_add;
    reg.rw_0 = 0;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD, (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
                              &(val->slv0_subadd), 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_DATAWRITE_SLV0,
                              &(val->slv0_data), 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_DATAWRITE_SLV0, lsm6dso32_mem_bank_set(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV0_ADD, LSM6DSO32_SLV0_SUBADD, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_slv0_add_t::rw_0, lsm6dso32_slv0_add_t::slave0, lsm6dso32_sh_cfg_write_t::slv0_add, lsm6dso32_sh_cfg_write_t::slv0_data, and lsm6dso32_sh_cfg_write_t::slv0_subadd.

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lsm6dso32_sh_data_rate_get()

int32_t lsm6dso32_sh_data_rate_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_shub_odr_t *	val
	)

Rate at which the master communicates.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of shub_odr in reg slv1_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9496 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv0_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    switch (reg.shub_odr)
    {
      case LSM6DSO32_SH_ODR_104Hz:
        *val = LSM6DSO32_SH_ODR_104Hz;
        break;
 
      case LSM6DSO32_SH_ODR_52Hz:
        *val = LSM6DSO32_SH_ODR_52Hz;
        break;
 
      case LSM6DSO32_SH_ODR_26Hz:
        *val = LSM6DSO32_SH_ODR_26Hz;
        break;
 
      case LSM6DSO32_SH_ODR_13Hz:
        *val = LSM6DSO32_SH_ODR_13Hz;
        break;
 
      default:
        *val = LSM6DSO32_SH_ODR_104Hz;
        break;
    }
 
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SH_ODR_104Hz, LSM6DSO32_SH_ODR_13Hz, LSM6DSO32_SH_ODR_26Hz, LSM6DSO32_SH_ODR_52Hz, LSM6DSO32_SLV0_CONFIG, LSM6DSO32_USER_BANK, and lsm6dso32_slv0_config_t::shub_odr.

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lsm6dso32_sh_data_rate_set()

int32_t lsm6dso32_sh_data_rate_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_shub_odr_t	val
	)

Rate at which the master communicates.[set].

Parameters

ctx	read / write interface definitions
val	change the values of shub_odr in reg slv1_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9461 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv0_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.shub_odr = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV0_CONFIG, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), and lsm6dso32_slv0_config_t::shub_odr.

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lsm6dso32_sh_master_get()

int32_t lsm6dso32_sh_master_get	(	stmdev_ctx_t *	ctx,
		uint8_t *	val
	)

Sensor hub I2C master enable.[get].

Parameters

ctx	read / write interface definitions
val	change the values of master_on in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9043 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    *val = reg.master_on;
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, and lsm6dso32_master_config_t::master_on.

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lsm6dso32_sh_master_set()

int32_t lsm6dso32_sh_master_set	(	stmdev_ctx_t *	ctx,
		uint8_t	val
	)

Sensor hub I2C master enable.[set].

Parameters

ctx	read / write interface definitions
val	change the values of master_on in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9007 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.master_on = val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), and lsm6dso32_master_config_t::master_on.

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lsm6dso32_sh_pass_through_get()

int32_t lsm6dso32_sh_pass_through_get	(	stmdev_ctx_t *	ctx,
		uint8_t *	val
	)

I2C interface pass-through.[get].

Parameters

ctx	read / write interface definitions
val	change the values of pass_through_mode in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9193 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    *val = reg.pass_through_mode;
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, and lsm6dso32_master_config_t::pass_through_mode.

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lsm6dso32_sh_pass_through_set()

int32_t lsm6dso32_sh_pass_through_set	(	stmdev_ctx_t *	ctx,
		uint8_t	val
	)

I2C interface pass-through.[set].

Parameters

ctx	read / write interface definitions
val	change the values of pass_through_mode in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9156 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.pass_through_mode = val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), and lsm6dso32_master_config_t::pass_through_mode.

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lsm6dso32_sh_pin_mode_get()

int32_t lsm6dso32_sh_pin_mode_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_shub_pu_en_t *	val
	)

Master I2C pull-up enable.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of shub_pu_en in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9110 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    switch (reg.shub_pu_en)
    {
      case LSM6DSO32_EXT_PULL_UP:
        *val = LSM6DSO32_EXT_PULL_UP;
        break;
 
      case LSM6DSO32_INTERNAL_PULL_UP:
        *val = LSM6DSO32_INTERNAL_PULL_UP;
        break;
 
      default:
        *val = LSM6DSO32_EXT_PULL_UP;
        break;
    }
 
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_EXT_PULL_UP, LSM6DSO32_INTERNAL_PULL_UP, LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, and lsm6dso32_master_config_t::shub_pu_en.

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lsm6dso32_sh_pin_mode_set()

int32_t lsm6dso32_sh_pin_mode_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_shub_pu_en_t	val
	)

Master I2C pull-up enable.[set].

Parameters

ctx	read / write interface definitions
val	change the values of shub_pu_en in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9073 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.shub_pu_en = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), and lsm6dso32_master_config_t::shub_pu_en.

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lsm6dso32_sh_read_data_raw_get()

int32_t lsm6dso32_sh_read_data_raw_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_emb_sh_read_t *	val
	)

Sensor hub output registers.[get].

Parameters

ctx	read / write interface definitions
val	union of registers from SENSOR_HUB_1 to SENSOR_HUB_18

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 8888 of file lsm6dso32_reg.c.

{
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SENSOR_HUB_1,
                             (uint8_t *) val, 18U);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_1, LSM6DSO32_SENSOR_HUB_BANK, and LSM6DSO32_USER_BANK.

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lsm6dso32_sh_reset_get()

int32_t lsm6dso32_sh_reset_get	(	stmdev_ctx_t *	ctx,
		uint8_t *	val
	)

Reset Master logic and output registers.[get].

Parameters

ctx	read / write interface definitions
val	change the values of rst_master_regs in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9431 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    *val = reg.rst_master_regs;
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, and lsm6dso32_master_config_t::rst_master_regs.

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lsm6dso32_sh_reset_set()

int32_t lsm6dso32_sh_reset_set

(

stmdev_ctx_t *

ctx

)

Reset Master logic and output registers.[set].

Parameters

ctx	read / write interface definitions

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9388 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.rst_master_regs = PROPERTY_ENABLE;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.rst_master_regs = PROPERTY_DISABLE;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), PROPERTY_DISABLE, PROPERTY_ENABLE, and lsm6dso32_master_config_t::rst_master_regs.

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lsm6dso32_sh_slave_connected_get()

int32_t lsm6dso32_sh_slave_connected_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_aux_sens_on_t *	val
	)

Number of external sensors to be read by the sensor hub.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of aux_sens_on in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 8954 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    switch (reg.aux_sens_on)
    {
      case LSM6DSO32_SLV_0:
        *val = LSM6DSO32_SLV_0;
        break;
 
      case LSM6DSO32_SLV_0_1:
        *val = LSM6DSO32_SLV_0_1;
        break;
 
      case LSM6DSO32_SLV_0_1_2:
        *val = LSM6DSO32_SLV_0_1_2;
        break;
 
      case LSM6DSO32_SLV_0_1_2_3:
        *val = LSM6DSO32_SLV_0_1_2_3;
        break;
 
      default:
        *val = LSM6DSO32_SLV_0;
        break;
    }
 
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_master_config_t::aux_sens_on, LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV_0, LSM6DSO32_SLV_0_1, LSM6DSO32_SLV_0_1_2, LSM6DSO32_SLV_0_1_2_3, and LSM6DSO32_USER_BANK.

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lsm6dso32_sh_slave_connected_set()

int32_t lsm6dso32_sh_slave_connected_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_aux_sens_on_t	val
	)

Number of external sensors to be read by the sensor hub.[set].

Parameters

ctx	read / write interface definitions
val	change the values of aux_sens_on in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 8917 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.aux_sens_on = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_master_config_t::aux_sens_on, LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, and lsm6dso32_write_reg().

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lsm6dso32_sh_slv0_cfg_read()

int32_t lsm6dso32_sh_slv0_cfg_read	(	stmdev_ctx_t *	ctx,
		lsm6dso32_sh_cfg_read_t *	val
	)

Configure slave 0 for perform a read.[set].

Parameters

ctx	read / write interface definitions
val	Structure that contain uint8_t slv1_add; 8 bit i2c device address uint8_t slv1_subadd; 8 bit register device address uint8_t slv1_len; num of bit to read

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9597 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv0_add_t slv0_add;
  lsm6dso32_slv0_config_t slv0_config;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    slv0_add.slave0 = val->slv_add;
    slv0_add.rw_0 = 1;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD,
                              (uint8_t *)&slv0_add, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
                              &(val->slv_subadd), 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG,
                             (uint8_t *)&slv0_config, 1);
  }
 
  if (ret == 0)
  {
    slv0_config.slave0_numop = val->slv_len;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG,
                              (uint8_t *)&slv0_config, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV0_ADD, LSM6DSO32_SLV0_CONFIG, LSM6DSO32_SLV0_SUBADD, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_slv0_add_t::rw_0, lsm6dso32_slv0_add_t::slave0, lsm6dso32_slv0_config_t::slave0_numop, lsm6dso32_sh_cfg_read_t::slv_add, lsm6dso32_sh_cfg_read_t::slv_len, and lsm6dso32_sh_cfg_read_t::slv_subadd.

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lsm6dso32_sh_slv1_cfg_read()

int32_t lsm6dso32_sh_slv1_cfg_read	(	stmdev_ctx_t *	ctx,
		lsm6dso32_sh_cfg_read_t *	val
	)

Configure slave 0 for perform a write/read.[set].

Parameters

ctx	read / write interface definitions
val	Structure that contain uint8_t slv1_add; 8 bit i2c device address uint8_t slv1_subadd; 8 bit register device address uint8_t slv1_len; num of bit to read

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9652 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv1_add_t slv1_add;
  lsm6dso32_slv1_config_t slv1_config;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    slv1_add.slave1_add = val->slv_add;
    slv1_add.r_1 = 1;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_ADD,
                              (uint8_t *)&slv1_add, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_SUBADD,
                              &(val->slv_subadd), 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG,
                             (uint8_t *)&slv1_config, 1);
  }
 
  if (ret == 0)
  {
    slv1_config.slave1_numop = val->slv_len;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG,
                              (uint8_t *)&slv1_config, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV1_ADD, LSM6DSO32_SLV1_CONFIG, LSM6DSO32_SLV1_SUBADD, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_slv1_add_t::r_1, lsm6dso32_slv1_add_t::slave1_add, lsm6dso32_slv1_config_t::slave1_numop, lsm6dso32_sh_cfg_read_t::slv_add, lsm6dso32_sh_cfg_read_t::slv_len, and lsm6dso32_sh_cfg_read_t::slv_subadd.

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lsm6dso32_sh_slv2_cfg_read()

int32_t lsm6dso32_sh_slv2_cfg_read	(	stmdev_ctx_t *	ctx,
		lsm6dso32_sh_cfg_read_t *	val
	)

Configure slave 0 for perform a write/read.[set].

Parameters

ctx	read / write interface definitions
val	Structure that contain uint8_t slv2_add; 8 bit i2c device address uint8_t slv2_subadd; 8 bit register device address uint8_t slv2_len; num of bit to read

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9707 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv2_add_t slv2_add;
  lsm6dso32_slv2_config_t slv2_config;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    slv2_add.slave2_add = val->slv_add;
    slv2_add.r_2 = 1;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_ADD,
                              (uint8_t *)&slv2_add, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_SUBADD,
                              &(val->slv_subadd), 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG,
                             (uint8_t *)&slv2_config, 1);
  }
 
  if (ret == 0)
  {
    slv2_config.slave2_numop = val->slv_len;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG,
                              (uint8_t *)&slv2_config, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV2_ADD, LSM6DSO32_SLV2_CONFIG, LSM6DSO32_SLV2_SUBADD, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_slv2_add_t::r_2, lsm6dso32_slv2_add_t::slave2_add, lsm6dso32_slv2_config_t::slave2_numop, lsm6dso32_sh_cfg_read_t::slv_add, lsm6dso32_sh_cfg_read_t::slv_len, and lsm6dso32_sh_cfg_read_t::slv_subadd.

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lsm6dso32_sh_slv3_cfg_read()

int32_t lsm6dso32_sh_slv3_cfg_read	(	stmdev_ctx_t *	ctx,
		lsm6dso32_sh_cfg_read_t *	val
	)

Configure slave 0 for perform a write/read.[set].

Parameters

ctx	read / write interface definitions
val	Structure that contain uint8_t slv3_add; 8 bit i2c device address uint8_t slv3_subadd; 8 bit register device address uint8_t slv3_len; num of bit to read

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9762 of file lsm6dso32_reg.c.

{
  lsm6dso32_slv3_add_t slv3_add;
  lsm6dso32_slv3_config_t slv3_config;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    slv3_add.slave3_add = val->slv_add;
    slv3_add.r_3 = 1;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_ADD,
                              (uint8_t *)&slv3_add, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_SUBADD,
                              &(val->slv_subadd), 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG,
                             (uint8_t *)&slv3_config, 1);
  }
 
  if (ret == 0)
  {
    slv3_config.slave3_numop = val->slv_len;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG,
                              (uint8_t *)&slv3_config, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_SLV3_ADD, LSM6DSO32_SLV3_CONFIG, LSM6DSO32_SLV3_SUBADD, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), lsm6dso32_slv3_add_t::r_3, lsm6dso32_slv3_add_t::slave3_add, lsm6dso32_slv3_config_t::slave3_numop, lsm6dso32_sh_cfg_read_t::slv_add, lsm6dso32_sh_cfg_read_t::slv_len, and lsm6dso32_sh_cfg_read_t::slv_subadd.

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lsm6dso32_sh_status_get()

int32_t lsm6dso32_sh_status_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_status_master_t *	val
	)

Sensor hub source register.[get].

Parameters

ctx	read / write interface definitions
val	union of registers from STATUS_MASTER to

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9814 of file lsm6dso32_reg.c.

{
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_MASTER,
                             (uint8_t *) val, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_STATUS_MASTER, and LSM6DSO32_USER_BANK.

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lsm6dso32_sh_syncro_mode_get()

int32_t lsm6dso32_sh_syncro_mode_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_start_config_t *	val
	)

Sensor hub trigger signal selection.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of start_config in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9260 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    switch (reg.start_config)
    {
      case LSM6DSO32_EXT_ON_INT2_PIN:
        *val = LSM6DSO32_EXT_ON_INT2_PIN;
        break;
 
      case LSM6DSO32_XL_GY_DRDY:
        *val = LSM6DSO32_XL_GY_DRDY;
        break;
 
      default:
        *val = LSM6DSO32_EXT_ON_INT2_PIN;
        break;
    }
 
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_EXT_ON_INT2_PIN, LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, LSM6DSO32_XL_GY_DRDY, and lsm6dso32_master_config_t::start_config.

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lsm6dso32_sh_syncro_mode_set()

int32_t lsm6dso32_sh_syncro_mode_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_start_config_t	val
	)

Sensor hub trigger signal selection.[set].

Parameters

ctx	read / write interface definitions
val	change the values of start_config in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9223 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.start_config = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), and lsm6dso32_master_config_t::start_config.

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lsm6dso32_sh_write_mode_get()

int32_t lsm6dso32_sh_write_mode_get	(	stmdev_ctx_t *	ctx,
		lsm6dso32_write_once_t *	val
	)

Slave 0 write operation is performed only at the first sensor hub cycle.[get].

Parameters

ctx	read / write interface definitions
val	Get the values of write_once in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9344 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    switch (reg.write_once)
    {
      case LSM6DSO32_EACH_SH_CYCLE:
        *val = LSM6DSO32_EACH_SH_CYCLE;
        break;
 
      case LSM6DSO32_ONLY_FIRST_CYCLE:
        *val = LSM6DSO32_ONLY_FIRST_CYCLE;
        break;
 
      default:
        *val = LSM6DSO32_EACH_SH_CYCLE;
        break;
    }
 
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_EACH_SH_CYCLE, LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), LSM6DSO32_ONLY_FIRST_CYCLE, lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, and lsm6dso32_master_config_t::write_once.

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lsm6dso32_sh_write_mode_set()

int32_t lsm6dso32_sh_write_mode_set	(	stmdev_ctx_t *	ctx,
		lsm6dso32_write_once_t	val
	)

Slave 0 write operation is performed only at the first sensor hub cycle.[set].

Parameters

ctx	read / write interface definitions
val	change the values of write_once in reg MASTER_CONFIG

Return values

interface

status (MANDATORY: return 0 -> no Error)

Definition at line 9306 of file lsm6dso32_reg.c.

{
  lsm6dso32_master_config_t reg;
  int32_t ret;
 
  ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
 
  if (ret == 0)
  {
    ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                             (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    reg.write_once = (uint8_t)val;
    ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
                              (uint8_t *)&reg, 1);
  }
 
  if (ret == 0)
  {
    ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
  }
 
  return ret;
}

References LSM6DSO32_MASTER_CONFIG, lsm6dso32_mem_bank_set(), lsm6dso32_read_reg(), LSM6DSO32_SENSOR_HUB_BANK, LSM6DSO32_USER_BANK, lsm6dso32_write_reg(), and lsm6dso32_master_config_t::write_once.

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