Da Vinci Firmware 1
Firmware for the DaVinci-M rocket avionics board.
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stm32h7xx_it.c
Go to the documentation of this file.
1/* USER CODE BEGIN Header */
18/* USER CODE END Header */
19
20/* Includes ------------------------------------------------------------------*/
21#include "main.h"
22#include "stm32h7xx_it.h"
23/* Private includes ----------------------------------------------------------*/
24/* USER CODE BEGIN Includes */
25/* USER CODE END Includes */
26
27/* Private typedef -----------------------------------------------------------*/
28/* USER CODE BEGIN TD */
29
30/* USER CODE END TD */
31
32/* Private define ------------------------------------------------------------*/
33/* USER CODE BEGIN PD */
34
35/* USER CODE END PD */
36
37/* Private macro -------------------------------------------------------------*/
38/* USER CODE BEGIN PM */
39
40/* USER CODE END PM */
41
42/* Private variables ---------------------------------------------------------*/
43/* USER CODE BEGIN PV */
44
45/* USER CODE END PV */
46
47/* Private function prototypes -----------------------------------------------*/
48/* USER CODE BEGIN PFP */
49
50/* USER CODE END PFP */
51
52/* Private user code ---------------------------------------------------------*/
53/* USER CODE BEGIN 0 */
54
55/* USER CODE END 0 */
56
57/* External variables --------------------------------------------------------*/
58extern MDMA_HandleTypeDef hmdma_quadspi_fifo_th;
59extern QSPI_HandleTypeDef hqspi;
60extern TIM_HandleTypeDef htim6;
61extern TIM_HandleTypeDef htim7;
62extern TIM_HandleTypeDef htim13;
63extern DMA_HandleTypeDef hdma_usart1_rx;
64extern DMA_HandleTypeDef hdma_usart1_tx;
65extern UART_HandleTypeDef huart1;
66extern TIM_HandleTypeDef htim4;
67
68/* USER CODE BEGIN EV */
69
70/* USER CODE END EV */
71
72/******************************************************************************/
73/* Cortex Processor Interruption and Exception Handlers */
74/******************************************************************************/
78void NMI_Handler(void)
79{
80 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
81
82 /* USER CODE END NonMaskableInt_IRQn 0 */
83 /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
84 while (1)
85 {
86 }
87 /* USER CODE END NonMaskableInt_IRQn 1 */
88}
89
93void HardFault_Handler(void)
94{
95 /* USER CODE BEGIN HardFault_IRQn 0 */
96
97 /* USER CODE END HardFault_IRQn 0 */
98 while (1)
99 {
100 /* USER CODE BEGIN W1_HardFault_IRQn 0 */
101 /* USER CODE END W1_HardFault_IRQn 0 */
102 }
103}
104
108void MemManage_Handler(void)
109{
110 /* USER CODE BEGIN MemoryManagement_IRQn 0 */
111
112 /* USER CODE END MemoryManagement_IRQn 0 */
113 while (1)
114 {
115 /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
116 /* USER CODE END W1_MemoryManagement_IRQn 0 */
117 }
118}
119
123void BusFault_Handler(void)
124{
125 /* USER CODE BEGIN BusFault_IRQn 0 */
126
127 /* USER CODE END BusFault_IRQn 0 */
128 while (1)
129 {
130 /* USER CODE BEGIN W1_BusFault_IRQn 0 */
131 /* USER CODE END W1_BusFault_IRQn 0 */
132 }
133}
134
138void UsageFault_Handler(void)
139{
140 /* USER CODE BEGIN UsageFault_IRQn 0 */
141
142 /* USER CODE END UsageFault_IRQn 0 */
143 while (1)
144 {
145 /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
146 /* USER CODE END W1_UsageFault_IRQn 0 */
147 }
148}
149
153void DebugMon_Handler(void)
154{
155 /* USER CODE BEGIN DebugMonitor_IRQn 0 */
156
157 /* USER CODE END DebugMonitor_IRQn 0 */
158 /* USER CODE BEGIN DebugMonitor_IRQn 1 */
159
160 /* USER CODE END DebugMonitor_IRQn 1 */
161}
162
163/******************************************************************************/
164/* STM32H7xx Peripheral Interrupt Handlers */
165/* Add here the Interrupt Handlers for the used peripherals. */
166/* For the available peripheral interrupt handler names, */
167/* please refer to the startup file (startup_stm32h7xx.s). */
168/******************************************************************************/
169
173void DMA1_Stream0_IRQHandler(void)
174{
175 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
176
177 /* USER CODE END DMA1_Stream0_IRQn 0 */
178 HAL_DMA_IRQHandler(&hdma_usart1_rx);
179 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
180
181 /* USER CODE END DMA1_Stream0_IRQn 1 */
182}
183
187void DMA1_Stream1_IRQHandler(void)
188{
189 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
190
191 /* USER CODE END DMA1_Stream1_IRQn 0 */
192 HAL_DMA_IRQHandler(&hdma_usart1_tx);
193 /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
194
195 /* USER CODE END DMA1_Stream1_IRQn 1 */
196}
197
201void TIM4_IRQHandler(void)
202{
203 /* USER CODE BEGIN TIM4_IRQn 0 */
204
205 /* USER CODE END TIM4_IRQn 0 */
206 HAL_TIM_IRQHandler(&htim4);
207 /* USER CODE BEGIN TIM4_IRQn 1 */
208
209 /* USER CODE END TIM4_IRQn 1 */
210}
211
215void USART1_IRQHandler(void)
216{
217 /* USER CODE BEGIN USART1_IRQn 0 */
218
219 /* USER CODE END USART1_IRQn 0 */
220 HAL_UART_IRQHandler(&huart1);
221 /* USER CODE BEGIN USART1_IRQn 1 */
222
223 /* USER CODE END USART1_IRQn 1 */
224}
225
229void TIM8_UP_TIM13_IRQHandler(void)
230{
231 /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 0 */
232
233 /* USER CODE END TIM8_UP_TIM13_IRQn 0 */
234 HAL_TIM_IRQHandler(&htim13);
235 /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 1 */
236
237 /* USER CODE END TIM8_UP_TIM13_IRQn 1 */
238}
239
243void TIM6_DAC_IRQHandler(void)
244{
245 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
246
247 /* USER CODE END TIM6_DAC_IRQn 0 */
248 HAL_TIM_IRQHandler(&htim6);
249 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
250
251 /* USER CODE END TIM6_DAC_IRQn 1 */
252}
253
257void TIM7_IRQHandler(void)
258{
259 /* USER CODE BEGIN TIM7_IRQn 0 */
260
261 /* USER CODE END TIM7_IRQn 0 */
262 HAL_TIM_IRQHandler(&htim7);
263 /* USER CODE BEGIN TIM7_IRQn 1 */
264
265 /* USER CODE END TIM7_IRQn 1 */
266}
267
271void QUADSPI_IRQHandler(void)
272{
273 /* USER CODE BEGIN QUADSPI_IRQn 0 */
274
275 /* USER CODE END QUADSPI_IRQn 0 */
276 HAL_QSPI_IRQHandler(&hqspi);
277 /* USER CODE BEGIN QUADSPI_IRQn 1 */
278
279 /* USER CODE END QUADSPI_IRQn 1 */
280}
281
285void MDMA_IRQHandler(void)
286{
287 /* USER CODE BEGIN MDMA_IRQn 0 */
288
289 /* USER CODE END MDMA_IRQn 0 */
290 HAL_MDMA_IRQHandler(&hmdma_quadspi_fifo_th);
291 /* USER CODE BEGIN MDMA_IRQn 1 */
292
293 /* USER CODE END MDMA_IRQn 1 */
294}
295
296/* USER CODE BEGIN 1 */
297
298/* USER CODE END 1 */
main.h
: Header for main.c file. This file contains the common defines of the application.
QUADSPI_IRQHandler
void QUADSPI_IRQHandler(void)
This function handles QUADSPI global interrupt.
Definition stm32h7xx_it.c:271
TIM6_DAC_IRQHandler
void TIM6_DAC_IRQHandler(void)
This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts.
Definition stm32h7xx_it.c:243
htim13
TIM_HandleTypeDef htim13
Definition main.c:68
htim6
TIM_HandleTypeDef htim6
Definition main.c:66
DMA1_Stream0_IRQHandler
void DMA1_Stream0_IRQHandler(void)
This function handles DMA1 stream0 global interrupt.
Definition stm32h7xx_it.c:173
UsageFault_Handler
void UsageFault_Handler(void)
This function handles Undefined instruction or illegal state.
Definition stm32h7xx_it.c:138
HardFault_Handler
void HardFault_Handler(void)
This function handles Hard fault interrupt.
Definition stm32h7xx_it.c:93
huart1
UART_HandleTypeDef huart1
Definition main.c:72
MemManage_Handler
void MemManage_Handler(void)
This function handles Memory management fault.
Definition stm32h7xx_it.c:108
DMA1_Stream1_IRQHandler
void DMA1_Stream1_IRQHandler(void)
This function handles DMA1 stream1 global interrupt.
Definition stm32h7xx_it.c:187
hdma_usart1_rx
DMA_HandleTypeDef hdma_usart1_rx
Definition main.c:73
MDMA_IRQHandler
void MDMA_IRQHandler(void)
This function handles MDMA global interrupt.
Definition stm32h7xx_it.c:285
hmdma_quadspi_fifo_th
MDMA_HandleTypeDef hmdma_quadspi_fifo_th
Definition main.c:59
hdma_usart1_tx
DMA_HandleTypeDef hdma_usart1_tx
Definition main.c:74
NMI_Handler
void NMI_Handler(void)
This function handles Non maskable interrupt.
Definition stm32h7xx_it.c:78
TIM4_IRQHandler
void TIM4_IRQHandler(void)
This function handles TIM4 global interrupt.
Definition stm32h7xx_it.c:201
USART1_IRQHandler
void USART1_IRQHandler(void)
This function handles USART1 global interrupt.
Definition stm32h7xx_it.c:215
TIM8_UP_TIM13_IRQHandler
void TIM8_UP_TIM13_IRQHandler(void)
This function handles TIM8 update interrupt and TIM13 global interrupt.
Definition stm32h7xx_it.c:229
BusFault_Handler
void BusFault_Handler(void)
This function handles Pre-fetch fault, memory access fault.
Definition stm32h7xx_it.c:123
htim4
TIM_HandleTypeDef htim4
Definition stm32h7xx_hal_timebase_tim.c:28
TIM7_IRQHandler
void TIM7_IRQHandler(void)
This function handles TIM7 global interrupt.
Definition stm32h7xx_it.c:257
htim7
TIM_HandleTypeDef htim7
Definition main.c:67
DebugMon_Handler
void DebugMon_Handler(void)
This function handles Debug monitor.
Definition stm32h7xx_it.c:153
hqspi
QSPI_HandleTypeDef hqspi
Definition main.c:58
stm32h7xx_it.h
This file contains the headers of the interrupt handlers.